Assessor Resource

UEEEC0054
Provide gate array solutions for complex electronics systems

Assessment tool

Version 1.0
Issue Date: May 2024


This unit involves the skills and knowledge required to design and develop electronic systems using gate array technology.

It includes working safely, following gate array design brief and interpreting device specifications, using appropriate development software, testing operation and verifying compliance of the of the design against the final brief, and documenting design and development work.

No licensing, legislative or certification requirements apply to this unit at the time of publication.

You may want to include more information here about the target group and the purpose of the assessments (eg formative, summative, recognition)


Evidence Required

List the assessment methods to be used and the context and resources required for assessment. Copy and paste the relevant sections from the evidence guide below and then re-write these in plain English.

Evidence required to demonstrate competence in this unit must be relevant to and satisfy all of the requirements of the elements, performance criteria and range of conditions on at least two separate occasions and include:

constructing, inspecting and testing circuit gate array device and circuits in accordance with design brief and regulatory requirements

dealing with unplanned situations in accordance with workplace procedures in a manner that minimises risk to personnel and equipment

designing gate array system in accordance with workplace procedures

developing outlines of alternative designs and comparing advantages and disadvantages on each

developing the gate array design within the safety and functional requirements and budget limitations

documenting and presenting design effectively

implementing relevant work health and safety (WHS)/occupational health and safety (OHS) requirements, including the use of risk control measures

negotiating design alteration requests and obtaining approval for final gate array design system

verifying compliance of the design against the final brief.

Evidence required to demonstrate competence in this unit must be relevant to and satisfy all of the requirements of the elements, performance criteria and range of conditions and include knowledge of:

gate array fundamentals

hardware design language

programmable logic device (PLD), including:

types of PLDs

features of complex programmable logic device (CPLD) devices

features of field programmable gate array (FPGA) devices

input/output (I/O) logic family assignment for FPGA

relevant job safety assessments or risk mitigation processes

relevant WHS/OHS legislated requirements

relevant workplace documentation

relevant workplace policies and procedures.

Assessors must hold credentials specified within the Standards for Registered Training Organisations current at the time of assessment.

Assessment must satisfy the Principles of Assessment and Rules of Evidence and all regulatory requirements included within the Standards for Registered Training Organisations current at the time of assessment.

Assessment must occur in suitable workplace operational situations where it is appropriate to do so; where this is not appropriate, assessment must occur in simulated suitable workplace operational situations that replicate workplace conditions.

Assessment processes and techniques must be appropriate to the language, literacy and numeracy requirements of the work being performed and the needs of the candidate.

Resources for assessment must include access to:

a range of relevant exercises, case studies and/or simulations

relevant and appropriate materials, tools, equipment and personal protective equipment (PPE) currently used in industry

resources that reflect current industry practices in relation to designing and developing gate array systems

applicable documentation, including workplace procedures, equipment specifications, regulations, codes of practice and operation manuals.

Submission Requirements

List each assessment task's title, type (eg project, observation/demonstration, essay, assingnment, checklist) and due date here

Assessment task 1: [title]      Due date:

(add new lines for each of the assessment tasks)

Assessment Tasks

Copy and paste from the following data to produce each assessment task. Write these in plain English and spell out how, when and where the task is to be carried out, under what conditions, and what resources are needed. Include guidelines about how well the candidate has to perform a task for it to be judged satisfactory.

Range is restricted to essential operating conditions and any other variables essential to the work environment.

Non-essential conditions may be found in the UEE Electrotechnology Training Package Companion Volume Implementation Guide.

Designing and developing a gate array system must include at least the following:

three input/output (I/O) devices or functions

Evidence required to demonstrate competence in this unit must be relevant to and satisfy all of the requirements of the elements, performance criteria and range of conditions on at least two separate occasions and include:

constructing, inspecting and testing circuit gate array device and circuits in accordance with design brief and regulatory requirements

dealing with unplanned situations in accordance with workplace procedures in a manner that minimises risk to personnel and equipment

designing gate array system in accordance with workplace procedures

developing outlines of alternative designs and comparing advantages and disadvantages on each

developing the gate array design within the safety and functional requirements and budget limitations

documenting and presenting design effectively

implementing relevant work health and safety (WHS)/occupational health and safety (OHS) requirements, including the use of risk control measures

negotiating design alteration requests and obtaining approval for final gate array design system

verifying compliance of the design against the final brief.

Evidence required to demonstrate competence in this unit must be relevant to and satisfy all of the requirements of the elements, performance criteria and range of conditions and include knowledge of:

gate array fundamentals

hardware design language

programmable logic device (PLD), including:

types of PLDs

features of complex programmable logic device (CPLD) devices

features of field programmable gate array (FPGA) devices

input/output (I/O) logic family assignment for FPGA

relevant job safety assessments or risk mitigation processes

relevant WHS/OHS legislated requirements

relevant workplace documentation

relevant workplace policies and procedures.

Assessors must hold credentials specified within the Standards for Registered Training Organisations current at the time of assessment.

Assessment must satisfy the Principles of Assessment and Rules of Evidence and all regulatory requirements included within the Standards for Registered Training Organisations current at the time of assessment.

Assessment must occur in suitable workplace operational situations where it is appropriate to do so; where this is not appropriate, assessment must occur in simulated suitable workplace operational situations that replicate workplace conditions.

Assessment processes and techniques must be appropriate to the language, literacy and numeracy requirements of the work being performed and the needs of the candidate.

Resources for assessment must include access to:

a range of relevant exercises, case studies and/or simulations

relevant and appropriate materials, tools, equipment and personal protective equipment (PPE) currently used in industry

resources that reflect current industry practices in relation to designing and developing gate array systems

applicable documentation, including workplace procedures, equipment specifications, regulations, codes of practice and operation manuals.

Copy and paste from the following performance criteria to create an observation checklist for each task. When you have finished writing your assessment tool every one of these must have been addressed, preferably several times in a variety of contexts. To ensure this occurs download the assessment matrix for the unit; enter each assessment task as a column header and place check marks against each performance criteria that task addresses.

Observation Checklist

Tasks to be observed according to workplace/college/TAFE policy and procedures, relevant legislation and Codes of Practice Yes No Comments/feedback
Work health and safety (WHS)/occupational health and safety (OHS) requirements and workplace procedures for a given work area are identified and applied 
 
 
 
 
 
WHS/OHS risk control measures and workplace procedures for carrying out the design work are followed 
 
 
 
 
 
 
 
Gate array system design is presented and explained to client representative and/or relevant person/s 
 
 
 

Forms

Assessment Cover Sheet

UEEEC0054 - Provide gate array solutions for complex electronics systems
Assessment task 1: [title]

Student name:

Student ID:

I declare that the assessment tasks submitted for this unit are my own work.

Student signature:

Result: Competent Not yet competent

Feedback to student

 

 

 

 

 

 

 

 

Assessor name:

Signature:

Date:

Assessment Record Sheet

UEEEC0054 - Provide gate array solutions for complex electronics systems

Student name:

Student ID:

Assessment task 1: [title] Result: Competent Not yet competent

(add lines for each task)

Feedback to student:

 

 

 

 

 

 

 

 

Overall assessment result: Competent Not yet competent

Assessor name:

Signature:

Date:

Student signature:

Date: